A memory controller, generally connected to a memory module, writes data into or read data from the memory module. A currently prevailing memory module is a double-data-rate (DDR) module.
When a memory controller sends a write command, data is transmitted to a memory module to be stored therein. When the memory controller sends a read command, data is read from the memory module and transmitted to the memory controller for subsequent processing.
FIG. 1 shows a schematic diagram of signal connections between a memory controller and a memory module. Signals between a memory controller 100 and a DDR memory module 200 at least include: an external clock signal CLKext, address signals, command signals, data serial signals DQ0 to DQ7, and a data strobe signal DQS. The command signals include a write enable signal WE; the address signals include memory address signals A0 to A13, a row address strobe signal RAS, a column address strobe signal CAS.
Further, a DDR transaction comprises steps below. The memory controller 100 first sends out command and address signals, and the DDR memory module 200 acquires a command, e.g., a write command or a read command, according to the command signal. The DDR memory module 200 then prepares to store or output data.
In response to a write command, the data serial signals DQ0 to DQ7 along with the data strobe signal DQS are generated by the memory controller 200. The DDR memory module 200 then latches data carried by the data serial signals DQ0 to DQ7 according to the data strobe signal DQS generated by the memory controller 100, and writes the data into corresponding memory address in the DDR memory module 200.
A period from the memory module 200 receives the write command till the data is ready for output is referred to as CAS latency CL, which is known to the memory controller 100 at a startup test and is generally two external clock CLKext cycles (CL=2). That is, when the command is a write command, the DDR memory module 200 drives the data serial signals DQ0 to DQ7 after the CAS latency CL. At this point, the memory controller 100 latches the data serial signals DQ0 to DQ7 according to the data strobe signal DQS, and acquires data of corresponding memory addresses.
FIG. 2 shows a timing diagram of signals for a write command. When the DDR memory module 200 outputs data, the data strobe signal DQS and the data serial signals DQ0 to DQ7 are generated, and a frequency of the data strobe signal DQS is the same as that of the external clock CLKext. In contrast, before the DDR memory module 200 outputs data, the data strobe signal DQS is tri-stated at high impedance.
As shown in FIG. 2, at a time T0, address A0 to A13 and the read command are acquired from the address signal and the command signal, while no operation (NOP) is observed at other times. Since the CAS latency CL equals two external clock CLKext cycles (CL=2), the data strobe signal DQS becomes low-level from tri-state at a time T1, and switches between high-level and low-level between T2 and T4 to again become tri-state after T4. Further, after a period of a CAS latency CL that equals two external clock CLKext cycles (CL=2), the data serial signals DQ0 to DQ7 in sequence generate data D0, D1, D2 and D3 during T2 to T4. Therefore, the memory controller 100 is able to latch the data D0, D1, D2 and D3 of the data serial signals DQ0 to DQ7 according to rising and falling edges of the data strobe signal DQS. In general, the memory controller 100 is able to latch the data serial signals DQ0 to DQ7 after delaying a phase of the data strobe signal DQS by 90 degrees.
FIG. 3 shows a schematic diagram of a conventional memory controller. The memory controller 100 comprises a clock generator 102, a command generator 104, a write pointer 106, a read pointer 108, a first-in-first-out (FIFO) buffer 110 and a processing circuit 112.
An internal clock CLKin of the memory controller 100 has a same frequency as that of the external clock CLKext, however with a different phase. In other words, the phase of the data serial signals DQ0 to DQ7 outputted by the DDR memory module is different from that of the internal clock CLKin, meaning that the data serial signals DQ0 to DQ7 and the internal clock CLKin are non-synchronous.
To overcome the issue of the non-synchronous data internal and external data of the memory controller 100, the memory controller 100 is built-in with a FIFO buffer 110. The data of the data serial signals DQ0 to DQ7 is written into the FIFO buffer 110 according to the data strobe signal DQS, and the processing circuit 112 in the memory controller 100 reads the data in the FIFO buffer 110 according to the internal clock CLKin.
As shown in FIG. 3, the command generator 104 generates the address signals and the command signal according to the external clock CLKext, and the DDR memory module 200 writes data into the FIFO buffer 110 according to the data serial signals DQ0 to DQ7 and the data strobe signal DQS. The processing circuit 112 then generates a read signal Fetch according to the internal clock CLKin to the FIFO buffer 110, and reads in sequence the data Data from the FIFO buffer 110.
To effectively manage the FIFO buffer 110, the memory controller 100 further comprises a write pointer 106 and a read pointer 108, which are regarded as a counter. Each time the DDR memory module 200 writes data, a write count maintained by the write pointer 106 is incremented by one; similarly, each time the processing circuit 112 reads data, a read count maintained by the read pointer 108 is also incremented by one. That is, the write pointer 106 counts the number of data being written/stored into the FIFO buffer 110 according to the data strobe signal DQS, and the read pointer 108 counts the number of data being read from the FIFO buffer 110 according to the read signal Fetch.
FIGS. 4A to 4F show schematic diagrams of operations of a FIFO buffer. In the description below, the timing diagram in FIG. 3 is used as an example, and suppose that the FIFO buffer 110 has four layers, i.e., #00, #01, #10 and #11, each of which for storing data. Further, the write pointer 106 and the read pointer 108 are both binary counters, with respective write count and read count being “11” at beginning.
Referring to FIG. 4A, at the time T2 at a rising edge of the data strobe signal DQS, the data D0 is written into the 00 layer of the FIFO buffer 110. At this point, a write pointer 106 increments by one so that the write count Wptr becomes “00” to indicate the presence of valid data temporarily stored therein, whereas the read count Rptr of a read pointer 108 remains at “11” to indicate that no data is yet read. Referring to FIG. 4B, at a time T2′ at a falling edge of the data strobe signal DQS, the data D1 is written into the 01 layer of the FIFO buffer 01. At this point, the write pointer 106 increments by one so that the write count Wptr becomes “01” to indicate the presence of valid data temporarily stored therein, whereas the read count Rptr of a read pointer 108 remains at “11” to indicate that no data is yet read.
When a difference between the write count Wptr of the write pointer 106 and the read count Rptr of the read pointer 108 exceeds a predetermined value, e.g., 2, the processing circuit 112 begins to read the data in the FIFO buffer 110. Therefore, as shown in FIG. 4C, at the time T3 at a rising edge of the data strobe signal DQS, the data D2 is written into the 10 layer of the FIFO buffer 110. At this point, the write pointer 106 increments by one so that the write count Wptr becomes “10” to indicate the presence of valid data stored therein, while the data D0 is read to increment the read pointer 108 by one so that the read count Rptr becomes “00” to indicate that the data D0 is currently invalid data. Referring to FIG. 4D, at a time T3′ at a falling edge of the data strobe signal DQS, the data D3 is written into the 11 layer of the FIFO buffer 110. At this point, the write pointer 106 increments by one so that the write count Wptr becomes “11” to indicate the presence of valid data stored therein, while the data D1 is read to increment the read pointer 108 by one so that the read count Rptr becomes “01” to indicate that the data D1 is currently invalid data.
After the time T4, no more data is inputted into the FIFO buffer 110, and the data strobe data DQS stays inactive such that the write count Wptr of the write pointer 106 stays at “11”. Meanwhile, the processing circuit 112 continues to read the data in the FIFO buffer 110. Referring to FIG. 4E, when the data D2 is read, the read pointer 108 increments by one so that the read count Rptr becomes “10” to indicate that the data D2 is regarded as invalid data. Referring to FIG. 4F, when the data D3 is read, the read pointer 108 increments by one so that the read count Rptr becomes “11” to indicate that the data D3 is regarded as invalid data.
When the memory controller 100 again generates a read command, the read pointer 108 and the write pointer 106 operate similarly to the operations described above. Thus, the FIFO buffer 110 serves as a ring buffer, the write count Wptr of the write pointer 106 indicates a position of valid data which is just written into the FIFO buffer 110, and the read count Rptr of the read counter 108 indicates a position of invalid data which is just read out the FIFO buffer 110.
It is to be noted that, that memory controller 100 and the DDR memory module 200 are welded onto a circuit board (not shown), and signal connections thereof are achieved by layout traces on the circuit board. Inevitably, noises on the circuit board are resulted.
More specifically, when the memory controller 100 is not reading data and the data strobe signal DQS is at tri-state, an event that the data strobe signal DQS is interfered by noises to cause glitch shall result in the write pointer 106 incrementing by one, when in fact that no valid data is written into the FIFO buffer 110. Consequently, erroneous data is received by the processing circuit 112 to even lead to a severe system crash.